EDN

Models for high-voltage transistors in a standard CMOS process

Designers of electronics and communications systems are constantly faced with the challenge of integrating greater functionality on less silicon area. Many of the system blocks – such as power ...
EDN

Power dissipation in portables: Design considerations using low-power CMOS ICs

When a CMOS circuit is in an idle state there is still some static power dissipation–a result of leakage current through nominally off transistors. Both nMOS and pMOS transistors used in CMOS logic ...
Electronics Weekly

X-Fab adds 375V nmos and pmos super-junction transistors to BCD chip process

X-Fab Silicon Foundries has added 375V power transistors to the devices available from its 180nm deep trench isolation BCD-on-SoI platform chip fab. The second generation of its XT018 super-junction ...