Design-Reuse

Creating IP level test cases which can be reused at SoC level

We are in an era where time is very important for product delivery. For processor based SoC, we invest lot of time in creating test cases which could have been simply reused from IP level verification ...
Design-Reuse

Implementing C model integration using DPI in SystemVerilog

In the current era of machine learning and artificial intelligence, accelerator based SoCs have more complex processing of data and those circuits have software and design verification cycles. These ...
Semiconductor Engineering

Extending The Benefits Of UVM To Include AMS: An Update On Accellera’s UVM-AMS Standard Development

SoC teams can be divided up into design and verification groups. For digital designs, the Universal Verification Methodology (UVM), initially developed by Accellera and now standardized as IEEE 1800.2 ...
EDN

Inheritance and polymorphism of SystemVerilog OOP for UVM verification

This is the second part in a series of introductory articles on SystemVerilog (SV) object oriented programming (OOP). In the first article, we covered the basics of the class data type and the history ...
Electronic Design

11 Myths About Portable Stimulus

Breker CEO Adnan Hamid dispels myths surrounding Accellera’s new Portable Stimulus standard, which enables test portability between verification process elements and reuse across many projects. Modern ...