SAN FRANCISCO–While the transistor may be on the minds of many a process R&D engineer these days, back-end-of-line (BEOL) interconnect technology and the materials challenges there– namely integrating ...

Stacking chiplets vertically using short and direct wafer-to-wafer bonds can reduce signal delay to negligible levels, enabling smaller, thinner packages with faster memory/processor speeds and lower ...

With typical lot sizes of 25 wafers and finished wafer values ranging from $4,000 to $17,000, depending on complexity, a ...

Power consumption is a crucial consideration for all types of electronics. As critical power components used in a wide range of electronic products, power MOSFET and other types of power semiconductor ...

The Soitec Group and the SEZ Group have initiated a joint development program (JDP) intended to speed the industrialisation of next-generation strained silicon-on-insulator (sSOI) substrates. Under ...

VILLACH, Austria–The SEZ Group here this week rolled out a non-contact, double-sided wafer spin processor for cleaning applications in the front end of line (FEOL) processes. The single-wafer spin ...

Is Moore’s Law slowing down? Clearly, chipmakers are struggling to keep up with Moore’s Law these days. But one sometimes forgotten and critical technology could easily derail Moore’s Law–materials.